Delta-Sigma Modulation in Fractional-N Frequency Synthesis

Delta-Sigma Fractional-N Phase-Locked Loops

This paper presents a tutorial on delta-sigma fractional-N PLLs for frequency synthesis. The presentation assumes the reader has a working knowledge of integer-N PLLs. It builds on this knowledge by introducing the additional concepts required to understand ΔΣ fractional-N PLLs. After explaining the limitations of integerN PLLs with respect to tuning resolution, the paper introduces the delta-s...

Self-Dithered Digital Delta-Sigma Modulators for Fractional-N PLL

Digital delta-sigma modulators (DDSMs) applied in fractional-N frequency synthesizers suffer from spurious tones which undermine the synthesizer’s spectral purity. We propose a solution featuring no hardware overhead while achieving equivalent spur elimination effect as using LFSR-dithering. This method can be implemented on MASH and single-loop DDSMs of 3rdand 2nd-order. key words: Digital del...

A Reduced Complexity Low Voltage 1-Bit High-Order Digital Delta-Sigma Modulator for Fractional-N Frequency Synthesis

In this paper, a reduced complexity third-order digital delta-sigma modulator for fractional-N frequency synthesis is presented. The modulator consists of two sub-blocks and has a single bit output which makes it best for this application. A good shaping of quantization noise is achieved using a new architecture for a digital third-order delta-sigma modulator. The hardware required for this mod...

Multi-bit Delta-sigma Modulation Technique for Fractional-n Frequency Synthesizers by Woogeun Rhee

Reduced complexity, high performance digital delta-sigma modulator for fractional-N frequency synthesis

This paper presents the design consideration of high order digital AZ modulators used as modulus controller for fractional-N frequency synthesizer. A third-order MASH structure (MASH 1-2) is designed and implemented which allows for the input to operate over 75% of the input adder capacity. The number of the output levels is reduced to two bits. The circuit was verified through simulation, ASIC...